The present invention relates to an architecture of a microcomputer, particularly a RISC (Reduced Instruction Set Computer) type microcomputer and, more particularly, to a technology effective if applied to a microcomputer to be packaged in a device for controlling it.
Moreover, the present invention relates to a circuit for coded division such as a dividing circuit for a coded binary number of arbitrary length and multi-precision and, more particularly, to a technology effective if applied to a step division of the RISC type microcomputer.
The most serious bottleneck for reducing the number of machine cycles necessary for executing one instruction is known to be the decoding of the instruction. In order to speed up this decoding, it is know effective to adopt an instruction format of fixed length so that where the boundary of the instruction resides may be informed before a preceding instruction has been interpreted. In the so-called xe2x80x9cRISC type computerxe2x80x9d, most instructions are executed for one cycle by adopting the instruction format of fixed length and a pipe line of multiple steps. The conventional RISC computer has used a 32-bit instruction format without exception. This 32-bit fixed length instruction format is advantageous in that what register is to be read can be determined without decoding the operation code by fixing fields in the instruction formats of a source register and a destination register, and in that no alignment is required when an immediate value is decoded. On the contrary, the 32-bit fixed length instruction format requires 32 bits even no matter simple content of an instruction might be described. As a result, the number of bytes occupied by the instruction code is increased to raise a problem that the ratio of the memory area to be occupied by a program is accordingly increased. If the memory area occupied by the program is increased, a memory having a larger capacity has to be packaged to raise the cost of the microcomputer system, thus making it difficult to construct a system having an excellent performance ratio to the cost. Since the RISC processor is given an architecture for speeding up the executions of instructions by reducing the number of instructions, there arises a tendency that the undefined operation codes grow more for the instruction set. The multiplicity of the undefined operation codes deteriorates the code efficiency of the object program and degrades the memory using lower efficiency.
The preceding patent application for improving such memory using efficiency or code efficiency is exemplified by Japanese Patent Application No. 222203/1990 (corresponding to U.S. patent application having Ser. No. 07/748,779 filed on Aug. 22, 1991). This application discloses a concept that the instruction format has a shorter bit number than that of the data word length. In this case, however, we have found that the various problems have to be solved by adopting the fixed length instruction format having a shorter bit number than the data word length. For example, new measures for the data processing have to be examined on the case, in which immediate data having a bit number equivalent to the data word length are necessary, or on the manner for assigning a branch destination address such as an absolute address as to the enlarged program or system structure. On the other hand, the above-specified application has failed to take any consideration into a relation of a power of 2 between the data word length and the instruction word length. Thus, the application has failed to positively prevent such a misalignment, in which one instruction is present across one word boundary of the memory, to leave new items such as the memory using efficiency, the software program simplification or the processing rate unexamined.
As a dividing technology to be executed in the microcomputer or the like, on the other hand, there is well known a division method, in which the codes of the quotient and the remainder are determined from the code of a dividend and the code of a divisor to execute the division with the absolute value of the dividend by a recovering method or a recovered method until the codes of the quotient and the remainder are finally corrected. In recent years, there are disclosed in the coded division several circuits and methods for executing the divisions in the coded state without taking the absolute values of the dividend and the divisor. In case the division is to be executed with the coded dividend and divisor, either method basically adopts the following procedures. Specifically, in case the code of the dividend or partial remainder and the code of the divisor are equal, the result of subtraction of the divisor from the dividend or partial remainder is used as a new partial remainder. In case, on the other hand, the code of the dividend or partial remainder and the code of the divisor are different, the result of an addition of the divisor to the dividend or partial remainder is used as a new partial remainder. Thus, the quotient is determined by repeating the subtractions or additions sequentially. At this time, in case the dividend is positive or in case the dividend is not contained by the divisor, a correct answer can be achieved by executing some quotient or remainder corrections on the basis of those procedures. In case, however, the dividend is negative and in case the dividend is contained by the divisor, the quotient thus determined is smaller than the correct quotient by the value xe2x80x9c1xe2x80x9d having an LSB weight toward the smaller absolute value. This error is caused by deeming the code of the partial remainder as correct in case the negative dividend or the partial remainder is subjected to the aforementioned addition or subtraction so that the partial remainder takes a zero.
In order to eliminate this error, there have been devised several dividing circuits which are equipped with means for detecting that the partial remainder is zero to correct the quotient. In Japanese Patent Laid-Open No. 165326/1990, for example, there is disclosed a technique, in which the irrecoverable dividing means is equipped with a register, which is set when the arithmetic result (i.e., the partial remainder) on each line is zero and reset when the value 1 enters the least significant bit on each line of the dividend, so that the quotient and remainder are corrected by using the result of the register. According to this disclosure, a correct coded division is realized by detecting and correcting the case, in which the partial remainder is zero, by using the aforementioned set and reset register. In Japanese Patent Laid-Open No. 171828/1990, on the other hand, there is disclosed another technique for preventing an erroneous quotient bit from being outputted in case the dividend is negative, by detecting whether or not the partial remainder is zero at each step of determining the quotient bit. In Japanese Patent Laid-Open No. 160235/1984, moreover, there is disclosed a technique which is equipped with a hardware for detecting the case, in which the partial remainder is zero, so that the most significant bit of the partial remainder may be deemed as 1 if the dividend is negative and if the partial remainder becomes zero in the course of the division.
Thus, In the prior art for the division with the coded dividend and divisor, the quotient bit is corrected by detecting that the partial remainder is zero. According to this technique, whether or not the partial remainder is zero has to be decided each time it is determined, and these decisions have to be accomplished n-times if the divisor has n bits. Moreover, whether or not the partial remainder is zero is not determined until all bits are examined. Therefore, the necessity for a special purpose hardware is anticipated if one decision is to be speeded up.
An object of the present invention is to solve the various problems accompanying the adoption of a fixed length instruction format having a smaller bit number than that of a data word length. A more specific object of the present invention is to provide a microcomputer which can achieve one or plural items selected from: that neither the use of immediate data nor the assignment of an absolute address is restricted even if the bit number of the fixed length instruction format is less than that of the data word length; that a description such as a necessary displacement can be executed in the fixed length instruction format having a limited bit number; that a contribution is made to the prevention of a misalignment of the program arrangement on a memory; and that the code efficiency or memory using efficiency is improved better from the standpoint of the content of a supporting instruction.
Another object of the present invention is to provide a division circuit which can determine a correct quotient easily without detecting whether or not a partial remainder is 0 at each dividing step of determining a quotient bit even in case a dividend is negative. Still another object of the present invention is to provide a division circuit which can develop a division program without considering whether the dividend is positive or negative. A further object of the present invention is to provide a division circuit which can improve the dividing efficiency with a simple circuit structure.
The foregoing and other objects and novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
The representatives of the invention to be disclosed herein will be briefly summarized in the following.
(1) In a microcomputer adopting the general purpose register method, there is adopted a fixed length instruction format which has a smaller bit number than that of the maximum data word length fed to instruction execution means.
(2) In order that the bit number set in the fixed length instruction format may prevent a misalignment of a program on a memory, the fixed length instruction format and the maximum data word length may be set to a bit number of a power of 2. If the maximum data word length is 32 bits, for example, the instruction format is fixed to 16 bits.
(3) In case the aforementioned relation holds between the maximum word length of data and the bit number of the, instruction format, a plurality of instruction may be prefetched in a common cycle so as to fetch the instructions efficiently by making use of an internal bus of a bit number equal to that of the maximum data word length or to reduce the bus access number for the instruction fetch.
(4) In case the internal bus is shared between the data transfer and the instruction fetch, the pipe control may be executed to prefer the data fetch thereby to delay the whole instruction execution schedule including an instruction fetch conflicting with that data fetch, so as to simplify either a processing when the data fetch and the instruction fetch conflict or a post-processing caused by the former.
(5) In order to simply cope with the state, in which the uses of the general purpose registers in response to the instructions before and after the pipe-line execution, the pipe-line control may be executed, because the general purpose register method is adopted, by detecting the state, in which the uses of the general purpose registers in response to the plurality of instructions to be executed in the pipe-line manner conflict, on the basis of the information of a register assigned area contained in the instruction format, thereby to delay the execution of an instruction after the register conflicting state on the basis of the register conflicting state detected and the execution cycle number of the instruction to be preferentially executed.
(6) In order that the restriction on the bit number of the fixed length instruction format may not limit the use of immediate data, it is advisable to support the instruction containing a description for assigning the immediate data in a data relation for offsetting the value of a displacement relative to the value of a predetermined register.
(7) Even in the fixed length instruction format having a restricted bit number, the displacement necessary for the data processing or the bit number of the immediate data may be maximized to support an instruction for implicitly assigning a predetermined general purpose register which is fixed as an operand despite of having no register assigning field in the instruction.
(8) Even in the fixed length instruction format having a restricted bit number, likewise, the displacement necessary for the processing or the bit number of the immediate data may be maximized to support an instruction containing a description for reflecting the truth or falsity of the arithmetic result for a specified condition upon a predetermined status flag.
(9) A proper branch destination assigning displacement length is fixedly assigned in accordance with the kinds of branching instructions. For a 16 bit fixed length instruction format, the displacement of a condition branching instruction is fixed at 8 bits, and the displacements of a subroutine branching instruction and an unconditional branching instruction are fixed to 12 bits.
(10) In case a dividend is negative in a coded division, a preliminary processing is executed by subtracting the value xe2x80x9c1xe2x80x9d having a weight of the LSB of the dividend from the dividend. This dividend is an integer if its LSB weight is 1. In case the dividend is a number having a fixed point, no substantial influence will arise even if the division is executed by assuming it to be an integer. This is because the point may be later adjusted. Hence, there arises no actual harm even if the intermediate calculations are executed while deeming the dividend as an integer by assuming the weight of the LSB of the dividend to be 1. In the following description, the dividend will be deemed as an integer unless otherwise especially specified so.
(11) Noting that the code bit is 1 for a negative dividend and 0 for a positive or zero dividend, the subtraction of a code bit (i.e., the MSB) from the dividend is the subtraction of 1 from a negative dividend. This calculation can be deemed as a transformation from a negative integer in a complement expression of 2 to a complement expression of 1. In this way, the preliminary processing for the dividend can be executed without considering whether the dividend is positive or negative. FIG. 35 shows a transformation state, in which the number 1 is subtracted from a negative integer of 4 bits, for example. Since an extra 1 bit is necessary for transforming the minimum value of a complement of 2 of a finite bit number into a complement of 1, an extension of 1 bit is executed, if necessary. Since a partial remainder may be positive, the aforementioned transformation for a negative integer is extended all over integers to introduce a new integer expression. For example, an expression shown in FIG. 36 is adopted within a range of coded integers of 4 bits. If an arbitrary integer is expressed by a number ZZ which is calculated by subtracting 1 from that integer, the expression of the ZZ, which has been transformed by subtracting 1 from an integer using a complement of 2, can be deemed equal to a complement of 1 in an integer no more than 0 and can be expressed in an integer no less than 0 by a number which is smaller by 1 than the intrinsic value. At this time, the code bit of 0 is 1 as for a negative number.
(12) In order to hold the quotient and the partial remainder (or rest) in the procedure of the coded division, the quotient (or quotient bit) and the rest (or partial remainder) may be latched in single storage means such as one register so that the number of processing steps for transferring the quotient bit or partial remainder to be calculated or used for the calculations to the register or the like may be reduced.
(1) According to the means described above, the adoption of a 16 bit fixed length instruction format for a 32 bit data word length makes it possible to grasp the decision of where an instruction boundary resides, before a preceding instruction is completed, like the RISC machine of the prior art having the 32 bit fixed length instruction format in the point that the instruction format has the fixed length, thereby to warrant an advantage such as a simplification of the instruction decoding.
(2) The program capacity is smaller than that of the case, in which the 32 bit fixed length instruction format is adopted. Specifically, in the RISC architecture for speeding up the executions of instructions by reducing the kinds of them, there is a tendency that many undefined operation codes are in the instruction set. If the instruction length is halved at this time from that of the prior art, the using efficiency of the program memory is improved.
(3) The various problems intrinsic to the adoption of a fixed length instruction format having a smaller bit number than that of a data word length are solved by the facts: that neither the use of immediate data nor the assignment of an absolute address is restricted even If the bit number of the fixed length instruction format is less than that of the data word length; that a description such as a necessary displacement can be executed in the fixed length instruction format having a limited bit number; that a contribution is made to the prevention of a misalignment of the program arrangement on a memory; and that the code efficiency or memory using efficiency is improved better from the standpoint of the content of a supporting instruction.
(4) According to the means for the aforementioned coded division, the quotient is determined by: subtracting the value 1 having the weight of the LSB of a dividend from the dividend in case the dividend is negative; predicting the code of a quotient: adding and subtracting a divisor to and from the dividend or partial remainder while depending upon whether the exclusive OR between the code of the dividend or partial remainder and the code of the divisor is 0 or 1 to exemplify the quotient bit by the exclusive OR between the code of the partial remainder and the code of the divisor; and correcting the quotient of the complement of 1 into a complement of 2 in case the quotient is negative.
(5) In case the aforementioned dividend is negative, the subtraction of the value 1 having the weight of the LSB of the dividend from the dividend is equivalent to the preliminary processing for expressing the value 0 such that all the bits and the code bits are expressed by 1. This preliminary processing makes it unnecessary to detect that the partial remainder is 0 in case the dividend is negative. As a result, the divisions including the overflow check or the correction of the remainder can be controlled on the basis of information such as the code bit of the first dividend, the code bit of the partial remainder, the code bit of the divisor and the code bit of the quotient. This can simplify the hardware and software of the divisions and can effect an application to the coded divisions of arbitrary length and arbitrary accuracy. In addition, the register for latching the partial remainder can be shifted to a more significant side by 1 bit, and the processing for applying means for shifting in the quotient bit can be speeded up.